Semiconductor Informations
| 74LS374 Hitachi Semiconductor - Octal D-type Edge-triggered Flip-Flips(with three-state outputs) Unit: mm 24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89 1.27 Max 10 1.30 2.54 Min 5.08 Max 7.62 0.51 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° + 0.11 Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N Conforms 1.26 g Unit: mm 12.6 13 Max 20 11 1 10 5.5 0.80 Max 2.20 Max *0.22 ± 0.05 0.20 ± 0.04 0.20 7.80 + 0.30 1.15 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0 |
| 74LS374 Fairchild Semiconductor - 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops April 1986 Revised March 2000 DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance s |
| 74L74 Dual Positive Edge Triggered D Flip-Flop - National Semiconductor |
| 74LCX00 Low Voltage Quad 2-Input NAND Gate - Fairchild Semiconductor 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs December 2013 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs Features - 5V tolerant inputs - 2.3V 3.6V VCC specifications provided - 5.2ns tPD max. (VCC = 3.3V), 10 A ICC max. - Power down high impedance input |
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