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Part Number: K9GAG08U0E (16Gb), K9LBG08U0E(32Gb), K9HCG08U1E(64Gb)

Function : 16Gb E-die NAND Flash – Multi-Level-Cell (2bit/cell)

Package: 48TSOP1 Type

Manufacturer: Samsung

Image

Description

The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 1.2ms on the 8,628-byte page and an erase operation can be performed in typical 1.5ms on a (1M+54.5K)byte block. Data in the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9GAG08U0E′s extended reliability of P/E cycles which are presented in the Qualification report by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9GAG08U0E is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

Pinout

Features

1. Voltage Supply
– 3.3V Device : 2.7V ~ 3.6V

2. Organization
– Memory Cell Array : (2,076M x 110.49K) x 8bit
– Data Register : (8K + 436) x 8bit

3. Automatic Program and Erase
– Page Program : (8K + 436)Byte
– Block Erase : (1M + 54.5K)Byte

4. Page Read Operation
– Page Size : (8K + 436)Byte
– Random Read : 400μs(Max.)
– Serial Access : 30ns(Min.)

5. Memory Cell : 2bit / Memory Cell

6. Fast Write Cycle Time
– Program time : 1.2ms(Typ.)
– Block Erase Time : 1.5ms(Typ.)

K9GAG08U0E Datasheet

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Description

This family of devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically. The S25FL128S and S25FL256S products offer high densities coupled with the flexibility and fast performance required by a variety of embedded applications. They are ideal for code shadowing, XIP, and data storage.

The Spansion S25FL128S and S25FL256S devices are flash non-volatile memory products using:

1. MirrorBit technology – that stores two data bits in each memory array transistor

2. Eclipse architecture – that dramaticallyimproves program and erase performance

3. 65 nm process lithography