Part Number: SN74LS322AN

Function: 8-BIT SHIFT REGISTERS WITH SIGN EXTEND

Package: DIP, SOIC 20 Pin Type

Manufacturer: Motorola ( Freescale )

Image and Pinouts:

Description

The SN74LS322AN is 8-bit shift register with sign extend.

These 8-bit shift registers have multiplexed input/output data ports to accomplish full 8-bit datahandling in a single 20-pin package. Serial data may enter the shift-right register through either D0 or D1 inputs as selected by the data select pin. A serial output is also provided. Synchronous parallel loading is achieved by taking the register enable and the S/Pinputs low. This places the three-state input/output ports in the data input mode. Data is entered on the low-to-high clock transition.The data extend function repeats the sign in the QA flip-flopduring shifting. An overriding clear input clears the internal registers when taken low whether the outputs are enabled or off. The output enable does not affect synchronous operation of the register.

Features

1. Multiplexed Inputs/Outputs Provide Improved Bit Density

2. Sign Extend Function

3. Direct Overriding Clear

4. 3-State Outputs Drive Bus Lines Directly

Other data sheets are available within the file: SN54LS322AJ, SN74LS322ADW, SN74LS322, 74322

SN74LS322AN Datasheet PDF Download

Part Number: NPIC6C596A-Q100

Function: Power logic 8-bit shift register; open-drain outputs

Package: SO, TSSOP, DHVQFN 16 Pin Type

Manufacturer: NXP Semiconductors.

Pinouts:

 

Description

The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MRinput. A LOW on MRresets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input.

The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. Ifboth clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out onthe falling edge of SHCP. Data in the storage register drives the gate of the outputextended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW.

Features

1. Wide supply range 2.3 V to 5.5 V

2. Low RDSon

3. Eight Power EDNMOS transistor outputs of 100 mA continuous current

4. 250 mA current limit capability

5. Output clamping voltage 33 V

6. 30 mJ avalanche energy capability

7. Enhanced cascading for multiple stages

8. All registers cleared with single input

9. Low power consumption

Applications:

1. LED sign

2. Graphic status panel

3. Fault status indicator

NPIC6C596A-Q100 Datasheet PDF Download

Other data sheets are available within the file:

NPIC6C596AQ100, NPIC6C596ABQ-Q100, NPIC6C596AD-Q100, NPIC6C596APW-Q100