ADC10D1000QML-SP Datasheet – GSPS A/D Converter

Part Number: ADC10D1000QML-SP

Function: Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

Package: CCGA 376 pin Type

Manufacturer: Texas Instruments

Image and Pinouts:

ADC10D1000QML-SP datasheet



The ADC10D1000 is the latest advance in TI’s Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 Watts of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C.

The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two’s complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 Watts in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range.



• Low Power Consumption

• R/W SPI Interface for Extended Control Mode±

• Internally Terminated, Buffered, Differential Analog Inputs

• Test Patterns at Output for System Debug

• Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments

• Option of 1:2 Demuxed or 1:1 Non-Demuxed LVDS Outputs

• Auto-Sync Feature for Multi-Chip Systems

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