M5LV-512 Datasheet – Complex Programmable Logic Device

Part Number: M5LV-512

Function: 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)

Package: PQFP 160 Pin Type

Manufacturer: Lattice Semiconductor


M5LV-512 datasheet



1. High logic densities and I/Os for increased logic integration
(1) 128 to 512 macrocell densities
(2) 68 to 256 I/Os

2. Wide selection of density and I/O combinations to support most application needs
(1) 6 macrocell density options
(2) 7 I/O options
(3) Up to 4 I/O options per macrocell density
(4) Up to 5 density & I/O options for each package

3. Performance features to fit system needs
(1) 5.5 ns tPDCommercial, 7.5 ns tPDIndustrial
(2) 182 MHz fCNT
(3) Four programmable power/speed settings per block

4. Flexible architecture facilitates logic design
(1) Multiple levels of switch matrices allow for performance-based routing
(2) 100% routability and pin-out retention
(3) Synchronous and asynchronous clocking, including dual-edge clocking
(4) Asynchronous product- or sum-term set or reset
(5) 16 to 64 output enables
(6) Functions of up to 32 product terms

Other data sheets are available within the file: M5-128, M5-128/104-7YI, M5-128/120-7YC, M5-128/120-7YI, M5-128/68-7VC

M5LV-512 Datasheet PDF Download

M5LV-512 pdf