Part Number: SN65LVDS310
Function: PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
Package: 48 Pin BGA Type
Manufacturer: Texas Instruments
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Description
The SN65LVDS310 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS310 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.
Pinouts:
Features
1. Serial Interface Technology
2. Compatible With FlatLink™ 3G Transmitters (E.g., SN65LVDS305 or SN65LVDS307)
3. Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over One SubLVDS Differential Data Line
4. SubLVDS Differential Voltage Levels
5. Up to 405-Mbps Data Throughput
6. Three Operating Modes to Conserve Power
(1) Active mode QVGA: 17 mW
(2) Typical Shutdown: 0.7 µW
(3) Typical Standby Mode: 67 µW Typical
7. ESD Rating > 4 kV (HBM)
8. Pixel-Clock Range of 4 MHz–15 MHz
9. Failsafe on All CMOS Inputs
10. Packaged in 4-mm × 4-mm MicroStar Junior™µBGA® With 0,5-mm Ball Pitch
11. Very Low EMI
Applications
1. Small Low-Emission Interface Between
2. Graphics Controller and LCD Display
3. Mobile Phones and Smart Phones
4. Portable Multimedia Players
Other data sheets are available within the file: SN65LVDS310ZQCR, SN65LVDS310ZQCT
SN65LVDS310 Datasheet PDF Download
