Part Number: Pm25LD010

Function: 1 Mbit Serial Flash Memory

Package: SOP 8 Pin Type

Manufacturer: Chingis Technology

Description

The Pm25LD010 is 1Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers.

The Pm25LD512 / Pm25LD-010 / Pm25LD020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(Pm25LD020 is uniform 4 KByte sectors or uniform 64 KByte). The Pm25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures between -40°C to +105°C.

Ordering Informations:

 

1 Mbit Single Operating Voltage Serial Flash Memory

With 100 MHz Dual-Output SPI Bus Interface Pm25LD512/010/ 020

Features:

• Single Power Supply Operation – Low voltage range: 2.3 V – 3.6 V

• Memory Organization – Pm25LD512: 64K x 8 (512 Kbit) – Pm25LD010: 128K x 8 (1 Mbit) – Pm25LD020: 256K x 8 (2 Mbit) • Cost Effective Sector/Block Architecture – 512Kb : Uniform 4KByte sectors / Two uniform 32KByte blocks – 1Mb : Uniform 4KByte sectors / Four uniform 32KByte blocks – 2Mb : Uniform 4KByte sectors / Four uniform 64KByte blocks • Low standby current 1uA (Typ) • Serial Peripheral Interface (SPI) Compatible – Supports single- or dual-output – Supports SPI Modes 0 and 3 – Maximum 33 MHz clock rate for normal read – Maximum 100 MHz clock rate for fast read

• Page Program (up to 256 Bytes) Operation – Typical 2 ms per page program • Sector, Block or Chip Erase Operation – Maximum 10 ms sector, block or chip erase • Low Power Consumption – Typical 10 mA active read current – Typical 15 mA program/erase current • Hardware Write Protection – Protect and unprotect the device from write operation by Write Protect (WP#) Pin • Software Write Protection – The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as readonly • High Product Endurance – Guaranteed 200,000 program/erase cycles per single sector – Minimum 20 years data retention

• Industrial Standard Pin-out and Package – 8-pin 150mil SOIC – 8-pin 208mil SOIC for Pm25LD040 – 8-pin 300mil PDIP for Pm25LD040 – 8-contact WSON – 8-pin TSSOP – Lead-free (Pb-free), halogen-free package

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Pm25LD010 PDF Datasheet

Part Number: MX25L25635E

Function: 256M-Bit FLASH MEMORY

Package: SOP 16 Pin Type

Manufacturer: MACRONIX

Images:

Description

MX25L25635E is 268,435,456 bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

Note]

HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1532 REV. 0.01, NOV. 18, 2009 1 MX25L25635E Contents Features… 5 GENERAL Description.. 7 Table 1. Additional Features … 7 PIN CONFIGURATION. 8 PIN Description… 8 BLOCK DIAGRAM. … 9 DATA PROTECTION. .. 10 Table 2. Protected Area Sizes… 11 Table 3. 4K-bit Secured OTP Definition 11 Memory Organization. … 12 Table 4. Memory Organization. 12 DEVICE OPERATION. 13 Figure 1. Serial Modes Supported (for Normal Serial mode) 13 HOLD Features.. 14 Figure 2. Hold Condition Operation . 14 COMMAND Description. … 15 Table 5. Command Sets 15 (1) Write Enable (WREN).. […]

MX25L25635E is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.

MX25L25635E PDF Datasheet