Part Number: SN65LVDS310

Function: PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

Package: 48 Pin BGA Type

Manufacturer: Texas Instruments

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Description

The SN65LVDS310 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS310 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.

Pinouts:

Features

1. Serial Interface Technology

2. Compatible With FlatLink™ 3G Transmitters (E.g., SN65LVDS305 or SN65LVDS307)

3. Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over One SubLVDS Differential Data Line

4. SubLVDS Differential Voltage Levels

5. Up to 405-Mbps Data Throughput

6. Three Operating Modes to Conserve Power
(1) Active mode QVGA: 17 mW
(2) Typical Shutdown: 0.7 µW
(3) Typical Standby Mode: 67 µW Typical

7. ESD Rating > 4 kV (HBM)

8. Pixel-Clock Range of 4 MHz–15 MHz

9. Failsafe on All CMOS Inputs

10. Packaged in 4-mm × 4-mm MicroStar Junior™µBGA® With 0,5-mm Ball Pitch

11. Very Low EMI

Applications

1. Small Low-Emission Interface Between
2. Graphics Controller and LCD Display
3. Mobile Phones and Smart Phones
4. Portable Multimedia Players

Other data sheets are available within the file: SN65LVDS310ZQCR, SN65LVDS310ZQCT

SN65LVDS310 Datasheet PDF Download

 

Part Number: AD6642

Function: Dual IF Receiver

Package: 144-ball SP_BGA Type

Manufacturer: Analog Devices

Pinouts:

 

Description

The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two highperformance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

PRODUCT HIGHLIGHTS :

1. Two ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball SP_BGA package.

2. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.

3. LVDS digital output interface configured for low cost FPGA families.

4. 120 mW per ADC core power consumption.

5. Operation from a single 1.8 V supply.

6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting(offset binary or twos complement), NSR, power-down,test modes, and voltage reference mode.

7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

Features

1. 11-bit, 200 MSPS output data rate per channel
2. Integrated noise shaping requantizer (NSR)
3. Performance with NSR disabled
4. Low power: 0.62 W @ 185 MSPS
5. 1-to-8 integer clock divider
6. Internal ADC voltage reference
7. 1.75 V p-p analog input range (programmable to 2.0 V p-p)
8. Differential analog inputs with 800 MHz bandwidth
9. User-configurable built-in self-test (BIST) capability
10. Energy-saving power-down modes

Applications:

1. Communications

2. Diversity radio and smart antenna (MIMO) systems

3. Multimode digital receivers (3G)

4. I/Q demodulation systems

5. General-purpose software radios

Other data sheets are available within the file: AD6642BBCZ, AD6642BBCZRL, AD6642EBZ

AD6642 Datasheet PDF Download