Part Number: AD6643

Function: Dual IF Receiver

Package: 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP Type

Manufacturer: Analog Devices

Pinouts:

 

Description

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Features

1. 11-bit, 250 MSPS output data rate per channel

2. Performance with NSR enabled

3. Performance with NSR disabled

4. Total power consumption: 706 mW at 200 MSPS

5. 1.8 V supply voltages

6. Integer 1-to-8 input clock divider (625 MHz maximum input)
7. Internal ADC voltage reference

8. Differential analog inputs with 400 MHz bandwidth

9. 95 dB channel isolation/crosstalk

10. Energy saving power-down modes

Applications:

1. Communications

2. Diversity radio and smart antenna (MIMO) systems

3. Multimode digital receivers (3G)

4. WCDMA, LTE, CDMA2000

5. WiMAX, TD-SCDMA

6. I/Q demodulation systems

7. General-purpose software radios

Other data sheets are available within the file:

AD6643200EBZ, AD6643-250EBZ, AD6643BCPZ-200, AD6643BCPZ-250

AD6643 Datasheet PDF Download

Part Number: SN65LVDS822

Function: Flatlink LVDS Receiver

Package: VQFN (48) Type

Manufacturer: Texas Instruments

Image:

Description

The SN65LVDS822 is an advanced FlatLink low-voltage differential signal (LVDS) receiver designed on a modern CMOS process. The device has several unique features, including three selectable CMOS output slew rates, CMOS output voltage support of 1.8 V to 3.3 V, a pinout swap option, integrated differential termination (configurable), an automatic low-power mode, and deserialization modes of 4:27 and 2:27. The device is compatible with TI FlatLink™ transmitters such as the SN75LVDS83B, SN65LVDS93A, and standard industry LVDS transmitters that comply with TIA/EIA 644-A.

Block Diagram :

Features

1. 4:27 LVDS-to-CMOS Deserializer

2. Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600

3. Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes

4. Very Low EMI With 3-Way Selectable CMOS Slew Rate

 

SN65LVDS822 Datasheet PDF Download

Other data sheets are available within the file: LVDS822, 65LVDS822, SN65LVDS822RGZR