74HCT194D Datasheet – Bidirectional Universal Shift Register

Part Number: 74HCT194D

Function: 4-bit Bidirectional Universal Shift Register

Package: SOP 16 Pin Type

Manufacturer: Philips Electronics ( https://www.nxp.com/ )


74HCT194D datasheet



The 74HC194 / 74HCT194, 74HCT194D are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The functional characteristics of the 74HC194 / 74HCT194 4-bit bidirectional universal shift registers are indicated in the logic diagram and function table. The registers are fully synchronous.


1. Shift-left and shift-right capability

2. Synchronous parallel and serial data transfer

3. Easily expanded for both serial and parallel operation

4. Asynchronous master reset

5. Hold (“do nothing”) mode

6. Output capability: standard

7. ICC category : MSI


Other data sheets are available within the file:

74HC194, 74HC194N, 74HC194U, 74HCT194D

74HCT194D Datasheet PDF Download

74HCT194D pdf

74199 Datasheet – 8 Bit Shift Register, 24 Pin, SN74199N

Part Number: 74199

Function: 8-Bit Shift Register

Package: 24 Pin Dip  type

Manufacturer: TI, Signetics, Fairchild


74199 datasheet Shift Register


The 74199 is a parallel in, parallel out register featuring synchronous parallel load, shift right and hold modes. State chages are initiated by the rising edge of the clock. Serial entry into the first stage is via J and K inputs for maximum flexibility. Two clock inputs are provided and it is possible to use one as an inhibit. An asychronous Mast Reset ( MR ) input overrides all other inputs and clears the register.

The 74199 is an 8−bit shift register in a 24−Lead DIP type package compatible with most other TTL and MSI logic families. All inputs are buffered to lower the drive requirements to one normalized Series 74 load, and input clamping diodes minimize switching transients to simplify system design. maximum input clock frequency is typically 35Mhz and power dissipation is typically 360mW.

Parallel loading is accomplished by applying the eight bits of data and taking the shift/load control input low when the clock input is not inhibited. The data is loaded into the associated flip−flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

74199 pinout

1. Parallel In / Parallel Out
2. Synchronous Parallen load
3. Asynchronous overriding clear
4. JK entry to first stage

74199 Datasheet PDF




Other data sheets are available within the file: SN74199

Related articles across the web