Part Number: ADSP-2184N
Function: 0.3-2.2V; instruction rate 80MHz; DSP microcomputer
Package: 100-lead LQFP and 144-ball BGA Type
Manufacturer: Analog Devices
Pinouts:
Description
The ADSP-218xN, ADSP-2184N series consists of six single chip microcomputers optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN series members appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision.
PERFORMANCE
Features
1. 12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus
2. tained performance
3. Single-cycle instruction execution
4. Single-cycle context switch
5. 3-bus architecture allows dual operand fetches in every instruction cycle
7. Multifunction instructions
8. Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down condition
9. Low power dissipation in idle mode
INTEGRATION
Features
1. ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions
2. Up to 256K byte of on-chip RAM, configured
3. Up to 48K words program memory RAM
4. Up to 56K words data memory RAM
5.Dual-purpose program memoryfor both instruction and data storage
6. Independent ALU, multiplier/accumulator, and barrel shifter computational units
7. Two independent data address generators
8. Powerful program sequencer provides zero overhead looping conditional instruction execution
9. Programmable 16-bit interval timer with prescaler
SYSTEM INTERFACE
Features
1. Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
2. All inputs tolerate up to 3.6 V regardless of mode
3. 16-bit internal DMA port for high-speed access to on-chip
4. memory (mode selectable)
5. 4M-byte memory interface for storage of data tables and pro
6. gram overlays (mode selectable)
7. 8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
8. Programmable memory strobe and separate I/O memory
9. space permits “glueless” system design Programmable wait state generation
10. Two double-buffered serial ports with companding hardware and automatic data buffering
11. Automatic booting of on-chip program memory from byte wide external memory, for example, EPROM, or through internal DMA Port
12. Six external interrupts
13. 13 programmable flag pins provide flexible system signaling
14. UART emulation through software SPORT reconfiguration
15. ICE-Port™ emulator interface supports debugging in final systems
Other data sheets are available within the file:
ADSP-2184NBCA-320, ADSP-2184NBST-320, ADSP-2184NKCA-320, ADSP-2184NKST-320
ADSP-2184N Datasheet PDF Download
