U664B PDF Datasheet – 1.3 GHz, Frequency Divider

Part Number: U664B, TFKU664B

Function: Divider Up To 1.3GHZ

Package: DIP 8 Pin

Manufacturer: TFK, ETC


U664B datasheet pinout


A frequency divider is an electronic circuit or device that takes an input signal at a certain frequency and produces an output signal at a lower frequency by dividing the input frequency by a specific integer factor. Frequency dividers are commonly used in a wide range of electronic applications, including communications, signal processing, and timing control.

Frequency synthesis is a process in electronics and communications where a desired output frequency is generated from a stable reference frequency source. This is commonly used in various applications, including radios, telecommunications, radar systems, and other communication and signal processing devices.

The TELEFUNKEN IC used is available in different versions:

• Frequency divider + 64 for frequency sythesizes in TV-tuner.

• The U664B version is stable even without an input signal and does not oscillate.

• The U664BS version oscillates due to internal feedback when there is no input signal


1. High input sensitivity

2. Large operation frequency range

3. High dynamic stability

4. Low power dissipation


Block diagram

U664B block diagram


U664B PDF Datasheet

U664B pdf

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7490 Datasheet – Decade Conunter and Divider ( PDF )

Part Number: 7490

Function : Package Contains a Divide-by-Two and a Divide-by-Five Counter

Package: DIP 14 Pin Type

Manufacturer: National Semiconductor, ETC

Image and Pinout



Mode of operation

The device consists of 4 flip-flops which are connected internally to create one divide-by-2 and one divide-by-5 counters. All filp-flops have a common reset line controlled by two inputs MR1 and MR2. When both MR1 and MR2 are high the counters are cleared. Flip-flop 1 is not interally connected to the other stages, thus providing a variety of counter sequences :

a) Counting to 10 (BCD) : Output Q0 is connected to the Clock 1 input. The input pluses are applied to the Clock 0 input and the divided signal is extracted at Q3. The device counts in binary code up to 9, with the outputs returning to zero on the 10th clock pulse. Pins 2, 3 and 6, 7 must be grounded.

b) Divide by 2 and divide by 5 : Filp-flop 1 is used as a 2:1 divider and flip-flops 2, 3 and 4 are used as a 5:1 divider

Logic Diagram



7490 Datasheet


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