memory

AT24C08 Datasheet – 8K (1024 x 8) Serial EEPROM – ATMEL

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Part Number: AT24C08

Description

2-Wire 8K (1024 x 8)  Serial EEPROM

Package: DIP 8 Pin

Manufacturer: ATMEL Corporation

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AT24C08 eeprom atmel

Description

The AT24C08 provides 8192 bits of serial electrically erasable and programmable read only memory EEPROM) organized as 1024 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential.

AT24C08, 8K SERIAL EEPROM: The 8K is internally organized with 4 blocks of 256 pages of 4 bytes each. Random word addressing requires a 10-bit data word address.

The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects.

 

Pinout

AT24C08 datasheet pinout

Features

1. 2-Wire Serial Interface

2. Schmitt Trigger, Filtered Inputs for Noise Suppression

3. Bidirectional Data Transfer Protocol

4. 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

5. Write Protect Pin for Hardware Data Protection

 

AT24C08 Datasheet


 

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48LC16M16A2 Datasheet – 4Megx16x4banks, SDRAM – Micron

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Part Number: 48LC16M16A2, MT48LC16M16A2

Function: SDR SDRAM ( 4 Meg x 16 x 4 banks )

Package: 54-ball FBGA, 54-pin TSOP II

Manufacturer: Micron Technology

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48LC16M16A2 sdram micron

Description

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16 bits.

Pinout

48LC16M16A2 datasheet pinout

 

Features

1. PC100- and PC133-compliant

2. Fully synchronous; all signals registered on positive edge of system clock

3. Internal, pipelined operation; column address can be changed every clock cycle

4. Internal banks for hiding row access/precharge

5. Programmable burst lengths: 1, 2, 4, 8, or full page

6. Auto precharge, includes concurrent auto precharge and auto refresh modes

7. Self refresh mode (not available on AT devices)

 

48LC16M16A2 Datasheet PDF


 

 

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