74LS189 PDF Datasheet – 64-BIT, Random Access Memory

This IC is a specific integrated circuit (IC) that belongs to the 74LS series of TTL (Transistor-Transistor Logic) logic chips. It is a 16×4-bit random access memory (RAM) chip, often used in digital systems for temporary data storage and retrieval.

Part Number: 74LS189

Function: 64-BIT RANDOM ACCESS MEMORY

Package: 16 Pin DIP, SMD type

Manufacturer: Fairchild Semiconductor

Image and Pinouts:

74LS189 datasheet ttl

Description

The 74LS189 is a high speed 64-bit RAM organized as a 16-word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are 3-state and are in the high impedance state whenever the chip select (CS) input is HIGH. The ouputs are active only in the read mode and the output is the complement of the stored data.

Block Diagram:

74LS189 datasheet ttl

Features:

1. 3-State ouputs for data bus applicatons

2. Buffered inputs minimize loading

3. Address decoding on-chip

4. Diode clamped inputs minimize ringing

74LS189 PDF Datasheet

49LF004B PDF – SST49LF004B – 4 Mbit SuperFlash Memory

Part Number: 49LF004B, SST49LF004B

Function: 4 Mbit, SuperFlash Memory

Package: PLCC 32, TSOP 32 Pin Type

Manufacturer: Silicon Storage Technology

Images:49LF004B pdf memory

Description

The 49LF004B flash memory device is designed to interface with host controllers (chipsets) that support a lowpin-count (LPC) interface for BIOS applications. The SST49LF004B device complies with Intel’s LPC Interface Specification 1.1, supporting single-byte Firmware Memory and LPC Memory cycle types.

The SST49LF004B is backward compatible to the SST49LF00xA Firmware Hub and the SST49LF0x0A LPC
Flash. In this document, FWH mode in the SST49LF00xA specification is referenced as the Firmware Memory Read/Write cycle and LPC mode in the SST49LF0x0A specification is referenced as the LPC Memory Read/Write cycle.

Two interface modes are supported by the SST49LF004B:LPC mode (Firmware Memory and LPC Memory cycletypes) for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.

Features

• SST49LF004B: 512K x8 (4 Mbit)

• Conforms to Intel LPC Interface Specification 1.1

– Supports Single-Byte LPC Memory and Firmware Memory Cycle Types

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 64 KByte overlay blocks

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption – Active Read Current: 6 mA (typical) – Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation – Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time: 8 seconds (typical)

• Two Operational Modes

– Low Pin Count (LPC) interface mode for in-system operation

– Parallel Programming (PP)  [ … ]

49LF004B pinout datasheet

49LF004B PDF Datasheet