Part Number: KLMAG2GE4A-A001

Function: e-MMC,16GB, Memory

Package: 169FBGA Type

Manufacturer: Samsung

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Description

The SAMSUNG e·MMC is an embedded MMC solution designed in a BGA package form. e·MMC operation is identical to a MMC card and therefore is a simple read and write to memory using MMC protocol v4.41 which is a industry standard.

e·MMC consists of NAND flash and a MMC controller. 3V supply voltage is required for the NAND area (VDDF) whereas 1.8V or 3V dual supply voltage (VDD) is supported for the MMC controller. Maximum MMC interface frequency of 52MHz and maximum bus widths of 8 bit are supported.

There are several advantages of using e·MMC. It is easy to use as the MMC interface allows easy integration with any microprocessor with MMC host. Any revision or amendment of NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to
faster product development as well as faster times to market.

The embedded flash mangement software or FTL(Flash Transition Layer) of e·MMC manages Wear Leveling, Bad Block Management and ECC. The FTL supports all features of the Samsung NAND flash and achieves optimal performance.

Pinouts:

Features:

1. MultiMediaCard System Specification Ver. 4.41 compatible. Detail description is referenced by JEDEC Standard

2. SAMSUNG e·MMC supports below special features which are being discussed in JEDEC

– High Priority Interrupt scheme is supported

– Back ground operation is supported.

3. Full backward compatibility with previous MultiMediaCard system ( 1bit data bus, multi-e·MMC systems)

4. Data bus width : 1bit (Default) , 4bit and 8bit

5. MMC I/F Clock Frequency : 0 ~ 52MHz

6. MMC I/F Boot Frequency : 0 ~ 52MHz

KLMAG2GE4A-A001 PDF Datasheet

Part Number: E8870DH

Function: DDR Memory Hub

Package: 567 pin OLGA Type

Manufacturer: Intel Corporation

Images:

Description

The DDR Memory Hub (DMH) is a memory translator hub that provides a mechanism for tunneling DDR SDRAM transactions between a Main Channel (RAMBUS* interface) and two Branch Channels (DDR SDRAM interfaces). While all RAMBUS signals maintain electrical compatibility with RDRAM pins, the RAMBUS signals are logically redefined to packetize DDR SDRAM I/O traffic. The DMH tunnels SDRAM packets between the Main Channel and a Branch Channel with deterministic timing. […]

Features

1. Two independent DDR DIMM channels per DMH.
(1) 4 DIMMs per DDR Channel.
(2) Registered PC1600 DDR DIMMs.

2. Write Buffers to minimize large turnaround times.

3. Pass through architecture for Read and Write accesses.

4. Supports 128 Mb, 256 Mb, 512 Mb and 1 Gb DDR SDRAM technologies.

5. Support of RDRAM CMOS signals to facilitate initialization and read/write of registers.

6. DMH internal registers accessed through CMOS signal interface.

7. Tunnels DDR SDRAM protocol over RSL.

8. Integrated System Management Bus (SMB) controller to read and write data from/to SPD EEPROM on the DIMMs

 

E8870DH PDF Datasheet