memory

K9F2G08U0B Datasheet – 256M x 8 Bit NAND Flash Memory

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Part Number: K9F2G08U0B

Function: 256M x 8 Bit NAND Flash Memory

Package: TSOP 48 Pin

Manufacturer: Samsung

Image

K9F2G08U0B datasheet

Description

Offered in 256Mx8bit, the K9F2G08U0B is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most costeffective solution for the solid state application market. A program operation can be performed in typical 200μs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input.

The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08X0B′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.

Pinout

K9F2G08U0B Pinout

 

Features

1. Voltage Supply
(1) 2.7V device(K9F2G08B0B): 2.50V ~ 2.90V
(2) 3.3V device(K9F2G08U0B): 2.70V ~ 3.60V

2. Organization
(1) Memory Cell Array : (256M + 8M) x 8bit
(2) Data Register : (2K + 64) x 8bit

3. Automatic Program and Erase
(1) Page Program : (2K + 64)Byte
(2) Block Erase : (128K + 4K)Byte

4. Page Read Operation
(1) Page Size : (2K + 64)Byte
(2) Random Read : 25µs(Max.)
(3) Serial Access : 25ns(Min.)

5. Command/Address/Data Multiplexed I/O Port

 

K9F2G08U0B Datasheet PDF Download

K9F2G08U0B pdf

Other data sheets are available within the file:  K9F2G08B0B-P, K9F2G08U0B, K9F2G08U0BP

EDI88512CA Datasheet PDF – 512Kx8 Monolithic SRAM

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Part Number: EDI88512CA

Function: 512Kx8 Monolithic SRAM, SMD 5962-95600

Package: DIP 32 Type, SOJ 36 Pin Type

Manufacturer: White Electronic Designs ( MicroSemi )

Image and Pinouts:

EDI88512CA datasheet

 

Description

The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 be come the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535.

 

Features

1. Access Times of 15, 17, 20, 25, 35, 45, 55ns

2. Data Retention Function (LPA version)

3. TTL Compatible Inputs and Outputs

4. Fully Static, No Clocks

5. Organized as 512Kx8

6. Commercial, Industrial and Military Temperature Ranges

Other data sheets are available within the file:

EDI88512CA15B32B, EDI88512CA15B32C, EDI88512CA15CB, EDI88512CA15CM

EDI88512CA Datasheet PDF Download


EDI88512CA pdf