This post explains for the Clock and Data Recovery.
The Part Number is AD800.
The Package is 20-Pin SMD or Cerdip Dip Pin Type.
The function of this semiconductor is Clock Recovery and Data Retiming Phase-Locked Loop.
Manufacturer: Analog Devices
Image and pinout :
The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively.
Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data.
1. Standard Products
(1) 44.736 Mbps – DS-3
(2) 51.84 Mbps – STS-1
(3) 155.52 Mbps – STS-3 or STM-1
2. Accepts NRZ Data, No Preamble Required
3. Recovered Clock and Retimed Data Outputs
4. Phase-Locked Loop Type Clock Recovery – No Crystal Required
5. Random Jitter: 20° Peak-to-Peak
6. Pattern Jitter: Virtually Eliminated
7. 10KH ECL Compatible
8. Single Supply Operation: –5.2 V or +5 V
9. Wide Operating Temperature
10. Range: –40°C to +85°C
Ordering Number : AD802-155BR , AD802-155KR