74F109 Datasheet PDF – Dual JK, Flip-Flop

Part Number: 74F109

Function: Dual JK Positive Edge-Triggered Flip-Flop

Package: DIP, SOP, SOIC 16 Pin type

Manufacturer: Fairchild Semiconductor

Pinouts:

74F109 datasheet

 

Description

The 74F109 consists of two high-speed, completely independent transition clocked JKflip-flops. The clocking operationis independent of rise and fall times of the clock waveform.
The JKdesign allows operation as a D-type flip-flop (referto F74 data sheet) by connecting the J and Kinputs.

Asynchronous Inputs :

1. LOW input to SD sets Q to HIGH level

2. LOW input to CD sets Q to LOW level

3. Clear and Set are independent of clock

4. Simultaneous LOW on CD and SD makes both Q and Q HIGH

Absolute Maximum Ratings :

1. Storage Temperature : – 65°C to +150°C

2. Ambient Temperature under Bias : – 55°C to +125°C

3. Junction Temperature under Bias : – 55°C to +175°C

4. VCC Pin Potential to Ground Pin : – 0.5V to +7.0V

5. Input Voltage (Note 2) : – 0.5V to +7.0V

6. Input Current (Note 2) : -30 mA to +5.0 mA

 

Other data sheets are available within the file:

74F109PC, 74F109SC, 74F109SCX, 74F109SJ

74F109 Datasheet PDF Download


74F109 pdf

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74HC173 Datasheet – Quad D-type Flip-Flop ( PDF )

Part Number: 74HC173

Function: Quad D-type flip-flop, positive-edge trigger, 3-state

Package: DIP, SOP 16 Pin Type

Manufacturer: Philips Electronics ( https://www.nxp.com/ )

Pinouts:

74HC173 datasheet

 

Description

The 74HC173 / 74HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The devices are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q0to Q3) and master reset (MR).

The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset (cleared) independently of any other input condition.

The 3-state output buffers are controlled by a 2-input NOR gate.

 

Features

1. Gated input enable for hold (do nothing) mode

2. Gated output enable control

3. Edge-triggered D-type register

4. Asynchronous master reset

5. Output capability: bus driver

6. ICC category: MSI

 

Other data sheets are available within the file:

74173, 74HC173DB, 74HC173PW, 74HC173U

74HC173 Datasheet PDF Download


74HC173 pdf