This post explains for the Supervisor.
The Part Number is HY510N.
The function of this semiconductor is PC Power Supply Supervisor.
Package: DIP, SOP 8 Pin Type
Preview images :
1. PGI I power good input pin
2. GND P Ground
3. FPL_N O fault protection latch output pin(open drain output)
4. PDON_N I protection detector function ON/OFF control input pin
5. V33 I 3.3V input pin
6. V5 I 5V input pin
7. VCC I Supply voltage / 12V input pin
8. PGO O power good output pin(open drain output)
The HY510N is PC Power Supply Supervisor. A PC power supply supervisor, also known as a power supply supervisor IC or PSU supervisor, is an integrated circuit (IC) or semiconductor device designed to monitor and control the power supply unit (PSU) in a personal computer or other electronic devices. These supervisors play a crucial role in ensuring the proper operation, safety, and reliability of the power supply and the overall system.
The device provides protection circuits, power good output (PGO), fault protection latch (FPL_N), and a protection detector function (PDON_N) control. It can minimize external components of switching power supply systems in personal computer. The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. When OVD or UVD detect the fault voltage level, the FPL_N is latched HIGH and PGO go low. The latch can be reset by PDON_N goo HIGH.
Power supply supervisors are crucial components for system reliability and safety, as they help prevent power-related issues that could lead to system instability, data corruption, or hardware damage.
1. The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level.
2. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level.
3. Both of the power good output (PGO) and fault protection latch (FPL_N) are Open Drain Output.
4. 75 ms time delay for UVD.
5. 300 ms time delay for PGO.
6. 38 ms for PDON_N input signal De–bounce.
7. 73 us for internal signal De–glitches.
8. 2.4 ms time delay for PDON_N turn-off FPL_N