HEF4007UBP Datasheet – Dual Complementary Pair and Inverter

Dual Complementary Pair and Inverter is an electronic structure that includes two comparative and opposing corpora and an inverter.

Part Number: HEF4007UB

Function: Dual Complementary Pair and Inverter

Package: DIP 14 Pin type

Manufacturer: Philips Semiconductor, NXP




The HEF4007UBP is a dual complementary pair and an inverter with access to each device. It has three n-channel and three p-channel enhancement mode MOS transistors.

It has three n-channel and three p-channel enhancement mode MOS transistors. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

Dual Complementary Pair

This includes two complementary MOSFET pairs. These pairs consist of one N-channel MOSFET and one P-channel MOSFET. This dual complementary pair can be used in a variety of applications, including analog switching, digital logic implementation, and signal processing.


This IC includes a single inverter. An inverter is a digital circuit element that inverts an input signal. For example, if the input is a logical ‘1’, the output will be a logical ‘0’, and vice versa.



• Fully static operation

• 5 V, 10 V, and 15 V parametric ratings

• Standardized symmetrical output characteristics

• Specified from -40 °C to +85 °C

• Complies with JEDEC standard JESD 13-B

• Inputs and outputs are protected against electrostatic effects

This part has an extended mode MOS characteristic characteristic of three n-content and three p-content, and the recommended V_DD power supply range is defined as 3 V to 15 V relative to V_SS (usually called support). Random user inputs should be connected to V_DD, V_SS or other inputs.


1. SP2, SP3: source connections to 2nd and 3rd p-channel transistors

2. DP1, DP2: drain connections from the 1st and 2nd p-channel transistors

3. DN1, DN2 drain connections from the 1st and 2nd n-channel transistors

4. SN2, SN3 source connections to the 2nd and 3rd n-channel transistors

5. DN/P3 common connection to the 3rd p-channel and n-channel transistor drains

6. G1 to G3 gate connections to n-channel and p-channel of the three transistor pairs



· High input impedance amplifiers

· Linear amplifiers

· (Crystal) oscillators

· High-current sink and source drivers

· High impedance buffers.

By integrating the dual complementary pair and inverter into a single chip, design flexibility and space efficiency can be maximized.

Other data sheets within the file: HEF4007UB, HEF4007UBD, HEF4007UBT


HEF4007UBP Datasheet PDF

HEF4007UBF pdf